The present invention relates to a semiconductor memory device and a method of manufacturing the same, particularly to a static random access memory (SRAM) having complementary MOS (CMOS) transistors and a method of manufacturing the same.
As semiconductor integrated circuits are fabricated in a higher integration and in a larger scale, a large scale integrated circuit (LSI) in which a high speed logic circuit and a mass storage memory are mounted on a single semiconductor chip has been generally used. In order to achieve a high speed operation of the semiconductor integrated circuit, it is effective to enhance an integration degree by a scale-down of MOS transistors. Moreover, it is also effective to increase the integration degree and to shorten an average length of the wiring layers by enhancing an integration degree of the wiring layers.
Particularly, a CMOS type memory cell using six MOS transistors has been nowadays used in a large number of CMOS SRAM cells because of its large operation margin and small holding current. However, since the CMOS SRAM cells have a wide memory cell area, a reduction in the memory cell area is required for the CMOS SRAM cells for the sake of the scale-down of devices.
The object of the present invention is to provide a semiconductor memory device having CMOS transistors and a method of manufacturing the same, which is capable of increasing an integration degree of wiring layers and achieving a scale-down of the device.
The semiconductor memory device of the present invention which comprises memory cells each of which includes two load transistors, two driver transistors and two transfer transistors, the semiconductor memory device comprising:
a semiconductor substrate in which transistors are formed;
a first interlayer dielectric formed on the semiconductor substrate;
first contact portions formed in the first interlayer dielectric; and
first wiring layers formed on the first interlayer dielectric,
wherein the first contact portions and the first wiring layers include metal layers made of refractory metal and refractory metal nitride layers.
According to the semiconductor memory device of the present invention, the first contact portions and the first wiring layers include at least the metal layers made of refractory metal and the refractory metal nitride layer. The metal layers and the nitride layers forming the first wiring layers are preferably continuous to the metal layers and nitride layers forming the first contact portions. Specifically, conductive layers concurrently formed with conductive layers of the first contact portions are also used as the first wiring layers, so that wiring layers having thin film thickness can be formed. Such wiring layers having thin film thickness have an ability to reduce a focus margin in patterning the wiring layers. Accordingly, an integration degree and yield of the first wiring layers can be increased.
It is preferable that the first wiring layers include node wiring layers for connecting impurity diffusion layers of load transistors and impurity diffusion layers of driver transistors, and pad layers for connecting first contact portions and second contact portions.
Each of the node wiring layers comprises a first node wiring layer for connecting an impurity diffusion layer of a first load transistor and an impurity diffusion layer of a first driver transistor interposing one of the first contact portions therebetween, and a second node wiring layer for connecting an impurity diffusion layer of a second load transistor and an impurity diffusion layer of a second driver transistor interposing one of the first contact portions therebetween.
It is preferable that the first wiring layers further include upper conductive layers formed by metal layers made of a refractory metal and refractory metal nitride layers. Adoption of such layer structure is preferable for enhancing a conductivity of the first wiring layers.
The first wiring layers may have conductive layers continuous to plug layers forming the first contact portions, in stead of the upper conductive layers formed of the metal layers made of the refractory metal and the refractory metal nitride layers.
The first contact portions may have insulating layers, which is continuous to a second interlayer dielectric, therein. In this case, the insulating layers may be formed in a formation step of the second interlayer dielectric.
A method of fabricating a semiconductor memory device of the present invention comprises following steps (a) to (e).
(a) forming memory cells each of which includes two load transistors, two driver transistors and two transfer transistors in predetermined regions of a semiconductor substrate;
(b) forming a first interlayer dielectric on the semiconductor substrate;
(c) forming first contact holes in the first interlayer dielectric;
(d) forming metal layers made of refractory metal and refractory metal nitride layers on surfaces of the first interlayer dielectric and the contact holes; and
(e) patterning the metal layers and the nitride layers on the first interlayer dielectric, thereby forming first wiring layers.
According to the method of manufacturing the semiconductor memory device, by the steps (d) and (e), the first wiring layers can be formed by the metal layers made of refractory metal and the refractory metal nitride layers, which are formed in the same step of forming conductive layers of the first contact portions (refractory metal layers and refractory metal nitride layers having a barrier function). Accordingly, the first wiring layers can be formed by simpler processes than a case of forming the first wiring layers by doped polysilicon layers or aluminum layers. Moreover, since the refractory metal layers and the refractory metal nitride layers can be formed to have thin thickness, a focus margin in patterning them can be reduced. Accordingly, integration degree and yield of the first wiring layers can be increased.
It is preferable that at least node wiring layers for connecting impurity diffusion layers of the load transistors and impurity diffusion layers of the driver transistors, and pad layers for connecting the first contact portions and second contact portions, are formed in the formation of the first wiring layers.
In the formation of the first wiring layers, upper conductive layers made of refractory metal layers and refractory metal nitride layers may be further formed on the refractory metal layers and the refractory metal nitride layers, in spite of an increase in film formation steps.
In the formation of the first wiring layers, upper conductive layers continuous to plug layers forming the first contact portions may further be formed in the same film formation step as that of forming the plug layers.
In the formation of the first contact portions, insulating layers may be formed in the first contact portions, in the same film formation step as forming a second interlayer dielectric.
The refractory metals should be metals selected from titanium, tungsten, cobalt, molybdenum or the like.